1. Field of the Invention
The invention relates to a method and apparatus for the programming and erasure of a memory cell made out of floating-gate transistors. It can be applied especially to non-volatile electrically erasable and programmable memories, for example, EEPROMs and flash EPROMs.
2. Discussion of the Related Art
The memory cells of EEPROMs and flash EPROMs make use of a technology using floating-gate transistors. For the programming or erasure of such a memory cell, it is desirable to produce high voltages typically in the range of 15 to 20 volts.
A memory cell of an EEPROM is formed by a floating-gate transistor (FIG. 1a) comprising a control gate 101, a floating gate 102, a source region 103, a drain region 104, an oxide layer 105 and a substrate region 106. The gate 102 is said to be floating because it has no contact with the exterior that imposes a potential on it. The control gate 101 is connected to a word line of the memory and the drain region 104 to a bit line of the memory. The structure shown in FIG. 1a shows that the oxide thickness 105 between the floating gate 102 and the substrate region 106 is very small. Typically the oxide thickness 105 is in the range of some nanometers. The small oxide thickness enables the passage of electrons at this position by tunnel effect.
To program a memory cell, a highly positive voltage is applied to the word line connected to the control gate 101 of the memory cell and a zero voltage is applied to the bit line connected to the drain region 104. The application of these voltages creates a high voltage through the narrow oxide layer 105 that results in the migration of electrons towards the floating gate 102 by tunnel effect. These electrons are trapped in the floating gate 102.
Conversely, to erase a memory cell, a highly positive voltage is applied to the bit line and a zero voltage to the word line. The migration of the electrons then occurs in the reverse direction and the floating gate 102 gets discharged.
During the transfer of electrons between the floating gate 102 and the drain region 104, it is necessary that the variation of the electrical field created between these two zones should not be excessively abrupt so as not to embrittle or even damage the oxide layer 105.
Consequently, a ramp generation circuit is used, enabling the voltage applied to the gate 101 or to the drain region 104 of the memory cell to be increased linearly.
There is the known method of programming or erasing a memory cell that consists of the production of a programming voltage Vpp shown in FIG. 1b. The voltage signal applied to the drain or to the control gate of the memory cell comprises three phases:
an initial bias of the supply voltage Vcc of the memory forming a first voltage plateau 111; PA1 a voltage ramp formed by a rising phase 112 during which the voltage climbs linearly up to a high voltage and a voltage plateau 113 in which the end of the charging (or discharging respectively) of the floating gate 102 takes place during the programming (or erasure respectively) of the memory cell. The slope of the rising phase 112 of the ramp is chosen so that the variation of the electrical field between the drain 104 and the floating gate 102 is not excessively fast and so as to limit the electron flux between these two regions; and PA1 a voltage drop 114 during which the voltage applied to the drain region 104 or the control gate 101 of the transistor of the memory cell returns to the value of the supply voltage Vcc of the memory.
An objective of the invention is to reduce the time needed to program or erase a memory cell without adversely affecting the quality of the cell.